HW-V5-ML550-UNI-G【PDF 32/88 页】EVALUATION PLATFORM VIRTEX-5

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Chapter 3: Hardware Description

V CC

V ADJ

U5

R

1 IN

ND

6

2:1 Mux

2

V CC

COM

5

3

GND

NC

4

R NOM

MAX4625

RNom = 84.5 K Ω

Margin Control

Data Latch

V CC

U26

8:1 Mux

VR_SEL0

VR_SEL1

VR_SEL2

VR_SEL3

4

5

12

13

1D

2D

3D

4D

U25

V CC

1Q

2Q

3Q

4Q

V CC

16

2

7

10

15

16

15

14

13

12

11

10

9

V CC

X2

X1

X0

X3

A

B

C

X4

X6

X

X7

X5

EN_8

NC

GND

1

2

3

4

5

6

7

8

STB_VCCINT1V0 9 CLK

FPGA_RESETB 1

CLR

8

GND

1Q

2Q

3Q

4Q

3

6

11

14

MAX4781EUE

D

SN74LV175AD

D

D

-10% -7.5%

-5%

-2.5%

+2.5% +5% +7.5% +10%

ug202_3_11_031406

Figure 3-9:

Margin Control Circuit Details

To activate the margin control circuitry FPGA_RESETB is driven High, the desired margin

resistor select data is setup on the VR_SEL[3:0] bus, and the data latch of the voltage

regulator of interest is strobed to capture the resistor select data. See Margin Control

Strobes in Table 3-9 . The latch output drives the analog mux switch select lines to cause

selection of the appropriate R ADJ resistor, which causes the regulator to adjust its output to

the selected margin voltage value.

Each regulator has a two-pin test point connector associated with it (pin 1 = V OUT and pin

2 = GND). To apply V OUT values other than the fixed set the voltage regulator can supply,

first disable the on-board voltage regulator using the inhibit jumper shown in Figure 3-8 ,

and then connect a bench-top power supply to the two-pin test point connector for that

voltage. This provides bench-top power to the power plane and also “back powers” the

output pin of the inhibited voltage regulator.

Note: Do not turn OFF the 5V power to the ML550 Development Board while a bench-top power

supply is ON and attached to the board in the manner described above. The voltage regulator can be

damaged if the output is reverse powered and the 5V input is removed. Always turn the bench-top

power supply OFF first, then turn the 5V power to the ML550 Development Board OFF.

Power Monitor Connector

Not shown in Figure 3-8 or Figure 3-9 is the voltage plane current measurement resistor.

Each voltage regulator is routed to its own 10 m Ω 1% 3W Kelvin current sense resistor. The

32

ML550 Networking Interfaces Platform

UG202 (v1.4) April 18, 2008

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